In such scan test, flipflops of the circuit are chained to a test register. After filling with a test pattern, the whole circuit is operated, synchronously or asynchronously. Then the contents of the test register are serially shifted out as a result pattern for further evaluation. Scan test of a static RAM memory along the above lines has been described in European Patent Application 88201501.9, priority date Jul. 13, 1988, corresponding to commonly owned U.S. application Ser. No. 376066, filed Jul. 5, 1989, herein incorporated by reference. The known system comprises as functional blocks the RAM-matrix, various control and other information registers, and address decoder. In particular, the known system to a large degree obviates the need for extensive external communication, in that the test evolves internally and self-controlled. There is a test scan chain which needs a relatively long test/result pattern, and in a more complicated circuit, in particular one that has various function blocks of different character, the generation of the test and its execution would take unbearably long.